1. Technical Field of the Invention
The present invention relates to circuits and more particularly, to a reference-free single ended clocked sense amplifier circuit, which in some embodiments is used in connection with a domino logic circuit.
2. Background Art
Domino circuits often require true and complementary data input signals to implement Boolean logic functions. While an inversion of the previous domino stage's output may suffice logically, it leads to functional race conditions. Specifically, a domino gate typically requires both its true and complementary inputs to have the same state (e.g., a logic low state) during a precharge phase. This requirement is violated if a simple inverter is placed at the output of the domino stage. To solve this problem, a fully dual-rail implementation (including true and complementary versions of the domino stage) is used.
For example, referring to FIG. 1, a prior art domino logic circuit 10 provides signals Out and Out* on conductors 14 and 16 as a function of an input signal A1 . . . An, where Out and Out* both have a logic low state during a precharge phase and are complementary during an evaluate phase. Out and/or Out* may be inputs to a next domino stage(s). Circuit 10 includes a true domino stage 18 and a complementary domino stage 20 (also called domino gates) and static stages 24 and 26. In the particular prior art embodiment illustrated, static stages 24 and 26 are inverters. In this disclosure, signals on conductors 28 and 30 are called domino stage intermediate signals (or INT). They are referred to as intermediate because they are not ready for the next domino stage because they have a logic high state rather than a logic low state in the precharge phase. Inverters 24 and 26 provide signals Out and Out* on conductors 14 and 16, respectively. In the example of circuit 10, the function of domino stage 18 is a NOR function, the result of which is inverted by inverter 24 to produce an OR function (i.e., where OUT is the logical OR of inputs A1 . . . An). The function of domino stage 20 is an OR function, the result of which is inverted by inverter 26 to produce a NOR function (i.e., OUT* is the complement of the logical OR of inputs A1 . . . An).
A disadvantage of circuit 10 is that it requires both a domino stage and a complementary domino stage, leading to approximately twice the area and power consumption.
Another potential disadvantage of circuit 10 is that complementary domino stage 20 includes stacked transistors which can cause significant delay in switching states. It is often the case that in the evaluation phase, one domino gate (e.g., the true gate) can change states significantly faster than the other gate (e.g., the complementary gate).
Now considering circuits from a different technology (e.g., memory technology), prior art sense amplifier 30 has two input signals and two output signals. The voltages of the output signals are indicative of voltages of the input signals. In some versions of sense amplifier 30, the inputs are a D input signal and a D* input signal, wherein in a precharge phase, D and D* have the same voltage and in an evaluate phase, D and D* may have a different voltage. In other versions of sense amplifier 30, one of the input signals (e.g., the input signal to the gate of transistor M2) is variable and the other signal (e.g., the input signal to the gate of transistor M3) is a reference signal (e.g., Vcc/2). In FIG. 2, Out* is at node N1 and Out is at node N2. However, depending on the circuit in which sense amplifier 30 is implemented, either node N1 or N2 may be Out and the other Out*.
The case in which the inputs are D and D* is considered first. Sense amplifier 30 includes p-channel field effect transistors (pFET transistors) M1, M2, M3, M4, and M5, and n-channel field effect transistors (nFET transistors) M6, M7, M8, and M9. Transistors M4, M7, M5 and M8 form a latch of cross-coupled inverters. The pFET and nFET transistors described herein may be metal oxide semiconductor (MOS) pFET and nFET transistors, or other types of FETs or other types of transistors (e.g., bi-polar). If during a precharge phase, the input signals D and D* and a clock signal (Clk) have a logic high voltage ("are high"), then nodes N1 and N2 and corresponding output signals Out* and Out are low (predischarged) through transistors M6 and M9. With clock high, transistor M1 is off. With nodes N1 and N2 low, transistors M7 and M8 are off. However, transistors M4 and M5 may be on and nodes N3 and N4 are pulled down (but not completely to Vss because pFET transistors are involved). However, current does not flow through transistors M4 and M5 because transistors M1, M2, and M3 are off. Transistor M1 is referred to as a clocked head current source transistor. Transistors M2 and M3 together are referred to as differential pair transistors. Transistors M4, M7, M5, and M8 form a cross-coupled inverter latch. Transistors M6 and M9 are predischarge transistors.
If during an evaluate phase, clock goes low, transistor M1 turns on and transistors M6 and M9 turn off. First, assume that input signal D goes low, while D* remains high. In that case, transistor M2 is turned on, while transistor M3 remains off. Nodes N1 and N3 will be pulled high. As node N1 rises, transistor M5 starts to turn off and transistor M8 starts to turn on. As transistor M8 starts to turn on, output signal Out is pinned low keeping transistor M4 on so that node N1 and the signal Out* can continue to be pulled high. This positive feedback loop provides hysteresis, which helps improve DC noise immunity. Second, assume that input signal D* goes low, while D remains high. In that case, transistor M3 is turned on, while transistor M2 remains off. Nodes N2 and N4 will be pulled high. As node N2 rises, transistor M4 starts to turn off and transistor M7 starts to turn on. As transistor M7 starts to turn on, output signal Out* is pinned low keeping transistor M5 on so that node N2 and the signal Out are pulled high.
In those versions with a reference voltage, if D is high, transistor M2 is off, but M3 is at least partially turned on and Out is pulled high. If D is low, more current flows through M2 than M3 and N1 is pulled up more than node N2 turning off M5 and turning on M8 to pull down Out.
Referring to FIG. 3, in a different prior art sense amplifier 36, nFET transistors replace pFET transistors and vice versa as compared to sense amplifier 30. Sense amplifier 36 includes a clocked tail current source transistor (M11), and differential pair transistors (M12 and M13) a cross-coupled inverters latch (M14, M17, M15, and M18), and precharge transistors (M16 and M19). Like with sense amplifier 30 of FIG. 2, in some versions of sense amplifier 36, the inputs to the gates of M12 and M13 are a D input signal and a D* input signal. In these versions, during precharge, Clk, D, and D* are low so Out and Out* and nodes N1, N2, N3, and N3 are pulled high. During the evaluate phase, Clk goes low and D and D* are differential. If D goes high, M12 is turned on pulling Out low. If D* goes high, M13 is turned on pulling Out* low.
In other versions of sense amplifier 36, one of the input signals is variable (e.g., to M12) and the other signal is a reference signal (e.g., Vcc/2) (e.g., to M13). The input signal is low during precharge and conditionally changes during an evaluate phase. In the evaluate phase, if D is less than the reference, Out* is pulled low. If D is greater than the reference Out is pulled low.